NV_GPU_PSTATE20_CLOCK_ENTRY_V1 Struct Reference

#include <nvapi.h>

Data Fields
NV_GPU_PUBLIC_CLOCK_ID	domainId
NV_GPU_PERF_PSTATE20_CLOCK_TYPE_ID	typeId
NvU32	bIsEditable:1
NvU32	reserved:31
NV_GPU_PERF_PSTATES20_PARAM_DELTA	freqDelta_kHz
union {
struct {
NvU32   freq_kHz
}   single
struct {
NvU32   minFreq_kHz
NvU32   maxFreq_kHz
NV_GPU_PERF_VOLTAGE_INFO_DOMAIN_ID   domainId
NvU32   minVoltage_uV
NvU32   maxVoltage_uV
}   range
}	data

Detailed Description

Used to describe single clock entry.

Field Documentation

NvU32 NV_GPU_PSTATE20_CLOCK_ENTRY_V1::bIsEditable

union { ... } NV_GPU_PSTATE20_CLOCK_ENTRY_V1::data

Clock domain type dependant information.

NV_GPU_PUBLIC_CLOCK_ID NV_GPU_PSTATE20_CLOCK_ENTRY_V1::domainId

ID of the clock domain.

NV_GPU_PERF_VOLTAGE_INFO_DOMAIN_ID NV_GPU_PSTATE20_CLOCK_ENTRY_V1::domainId

Voltage domain ID and value range in (uV) required for this clock.

NvU32 NV_GPU_PSTATE20_CLOCK_ENTRY_V1::freq_kHz

Clock frequency within given pstate in (kHz)

NV_GPU_PERF_PSTATES20_PARAM_DELTA NV_GPU_PSTATE20_CLOCK_ENTRY_V1::freqDelta_kHz

Current frequency delta from nominal settings in (kHz)

NvU32 NV_GPU_PSTATE20_CLOCK_ENTRY_V1::maxFreq_kHz

Max clock frequency within given pstate in (kHz)

NvU32 NV_GPU_PSTATE20_CLOCK_ENTRY_V1::maxVoltage_uV

NvU32 NV_GPU_PSTATE20_CLOCK_ENTRY_V1::minFreq_kHz

Min clock frequency within given pstate in (kHz)

NvU32 NV_GPU_PSTATE20_CLOCK_ENTRY_V1::minVoltage_uV

struct { ... } NV_GPU_PSTATE20_CLOCK_ENTRY_V1::range

NvU32 NV_GPU_PSTATE20_CLOCK_ENTRY_V1::reserved

These bits are reserved for future use (must be always 0)

struct { ... } NV_GPU_PSTATE20_CLOCK_ENTRY_V1::single

NV_GPU_PERF_PSTATE20_CLOCK_TYPE_ID NV_GPU_PSTATE20_CLOCK_ENTRY_V1::typeId

Clock type ID.

---

The documentation for this struct was generated from the following file:

• nvapi.h